Digital zero-phase restart circuit
US6307696A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1999 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | May 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An all digital timing loop is employed in a hard disk drive read channel for improved timing performance. Synchronizing the read channel to a sinewave preamble pattern at the beginning of a servo or data read operation is accomplished by first determining an accurate initial estimate of phase angle, and loading that phase value into the digital phase lock loop phase interpolator without having to halt and restart the sample clock. The timing loop synchronizes to the preamble input pattern very quickly so that timing overhead is reduced. The initial phase estimate is formed by accumulating even and odd ADC samples over a selected integration period, and using those values to access an arctan lookup table. Since ratios of even and odd ADC samples are used, gain variations and other analog tolerance issues are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.