Memory device, coupling noise eliminator, and coupling noise elimination method
US6307793A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2000 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory device having a plurality of memory cells arranged in matrix as a memory cell array, pull down transistors (21, 22) are formed on a write word line wrword0 where the write word line wrword0 is adjacent in configuration to a read word line rdword0. When the read word line rdword0 is a H level during data read from the memory cells, both the pull down transistors (21, 22) enter ON and the write word line wrword0 is set to a L level. Thereby, only a coupling noise voltage of a small magnitude is generated on the write word line wrword0 even if the read word line rdword0 adjacent to the write word line wrword0 is the H level. Because the coupling noise voltage generated is smaller than a threshold voltage Vth of a transfer gate (1) for data write of the memory cell, the transfer gate (1) cannot enter ON and no write error occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.