Clock and data recovery scheme for multi-channel data communications receivers
US6307906A · kind A · utility
114Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1998 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | Oct 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The multiple-channel clock and data recovery scheme of the present invention derives a single clock signal from multiple mis-matched data streams. The single clock is phased to provide a clocking signal such that the data sampler of the clock and data recovery scheme performs bit center sampling of the data at the bit center average of all channels. The phase of the recovery clock is the average of all the data stream phases, and is the optimal sampling phase for minimum combined bit error rate of all the channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.