On-chip cache file register for minimizing CPU idle cycles during cache refills
US6308241A · kind A · utility
5Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1997 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU has an execution unit for operating on data under instruction control. A cache and a buffer register are coupled in parallel to an input of the execution unit. The buffer register supplies an information item, such as data or an instruction, to the execution unit upon the cache having completed a refill process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.