Processor method and apparatus for performing single operand operation and multiple parallel operand operation
US6308252A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes n-bit (e.g., 128-bit) register circuitry for holding instruction operands. Instruction decode circuitry decodes processor instructions from an instruction stream. Arithmetic logic (AL) circuitry is operable to perform one of a single operation on at least one m-bit maximum (e.g., 64-bit) operand provided from the n-bit register circuitry, responsive to a first single processor instruction decoded by the instruction decode circuitry, wherein m<n. In addition, the AL circuitry is operable to perform multiple parallel operations on at least two portions of one n-bit operand provided from the n-bit register circuitry. The multiple parallel operations are performed responsive to a second single instruction decoded by the instruction decode circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.