Copper metallization structure and method of construction

US6309969A · kind A · utility

Assignee

• The John Hopkins University · US

Inventors

• Gerko Oskam · Baltimore, US
• Peter C. Searson · Baltimore, US
• Philippe M. Vereecken · Liège, BE
• John G. Long · Epsom, GB
• Peter Hoffmann · Senden, DE

Key dates

• Filing date: Nov 3, 1998
• Grant date: Oct 30, 2001
• Expiry date: Nov 3, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76879
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invention is directed to the use of copper as via and interconnect structures for an integrated circuit. The process in accordance with a preferred embodiment produces an interconnect layer of continuous copper with superior adhesion while requiring only a minimum number of steps for its production. This process addresses the current need in semiconductor manufacturing for reliable and performance-oriented vias and interconnect structures, while not being susceptible to many of the problems which plague the use of aluminum for similar structures. Fabrication of an integrated circuit in accordance with a preferred embodiment of the invention begins with the formation of semiconductor devices on a silicon wafer. Next, an intermetallic dielectric layer (IDL) is formed by materials such as silicon dioxide (SiO.sub.2), polymide, or silicon nitride over the devices. This step is followed by the laying of a diffusion barrier layer on the IDL surface. The resulting product is then exposed to an electrochemical deposition or electroplating stage for the formation of a copper layer directly on top of the diffusion barrier layer. In accordance with a preferred embodiment of the invention,…