Method to reduce wire-or glitch in high performance bus design to improve bus performance
US6310489A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1996 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Apr 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method of reducing wire-or glitch to improve bus speeds. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver is controlled. The off-going wave is forced to climb gradually such that one propagation delay of the loaded bus later, it is only marginally above a high threshold voltage. The fall time of the wave created by an on-going driver is minimized such that a strong negative going voltage propagates down the bus. This strong negative going voltage drags a composite wave on the bus (i.e. the combination of the waves of the on-going driver and the off-going driver) back below a low threshold voltage approximately one propagation delay after the switching occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.