Method and device for fast addressing redundant columns in a nonvolatile memory
US6310801A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2000 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Apr 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for addressing redundant columns in a nonvolatile memory, which receives, at inputs, selection addresses and comprises a plurality of redundant columns, each including a respective bit line and a plurality of memory cells connected to the bit line. The addressing method comprises the steps of: detecting a transition in the selection addresses; starting charging of all the bit lines upon detection of the transition in the addresses; then detecting whether one of the redundant columns is addressed; should one of the redundant columns be found to be addressed, proceeding with charging of the bit line of the redundant column addressed and interrupting charging of the bit lines of the redundant columns not addressed; and should none of the redundant columns be found to be addressed, interrupting charging of all the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.