Semiconductor memory device with redundant circuit
US6310806A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2000 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Nov 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundant memory circuit stores a defective row address. A switch circuit connects a spare row decoder with the wire for transmitting a row address signal according to the defective row address stored in the redundant memory circuit when the power supply is turned on. A row decoder deactivating circuit, when the power supply is turned on, deactivates the part of the row decoder corresponding to the defective row address according to the defective row address stored in the redundant memory circuit. As a result, when the row address buffer outputs the row address signal corresponding to the defective row address, the spare row decoder decodes the row address signal, thereby selecting a spare word line immediately.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.