Delay locking high speed clock synchronization method and circuit
US6310822A · kind A · utility
29Cited by
5References
46Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 7, 2000 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Feb 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock synchronizer circuit provides an internal clock signal for an integrated circuit that is synchronized to an external system clock signal, such that the internal clock integrated is aligned with and has minimal skew from the external system clock signal. The clock synchronizer circuit allows synchronizing of internal clocks of an integrated circuit with the external system clock having a period .tau..sub.ck less than the cumulative delay of internal receiving and distribution circuits of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.