Learn pending frame throttle
US6310874A · kind A · utility
7Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1998 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Mar 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L61/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Flow of data units to an address resolution processor is controlled to inhibit multiple data units from a single multicast flow from being enqueued with the address resolution processor. In a switch having a plurality of Input/Output Application Specific Integrated Circuits ("I/O ASICs") with a plurality of ports, no more than one data unit from each I/O ASIC is permitted to be enqueued with the address resolution processor at any point in time. A separate learn pending indicator may be defined for each I/O ASIC in the switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.