Single integrated circuit phase locked loop for synthesizing high-frequency signals for wireless communications and method for operating same
US6311050A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1998 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | May 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/199
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. The invention disclosed avoids the need for a traditional varactor implementation in the VCO, for a traditional large capacitor component in the loop filter, and for component trimming during processing and thereby provides a high-frequency frequency synthesizer that may be fully integrated on a single chip except for an external inductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.