Design of microelectronic process flows for manufacturability and performance
US6311096A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1999 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Apr 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q10/06
- WIPO fieldIT methods for management
- WIPO sectorElectrical engineering
Abstract
A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the sequential and stochastic nature of semiconductor manufacturing and enables the separation of device and process models, statistical modeling of process modules from observable wafer states and approximations for statistical optimization over large design spaces. The statistical estimation component of this method results in extremely accurate predictions of the variability of transistor performance for all of the fabricated flows. Statistical optimization results in devices that achieve all transistor performance and reliability goals and reduces the variability of key transistor performances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.