Semiconductor memory device and production method of the same
US6313539A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1998 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Dec 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: a capacitor formed on a substrate and including a lower electrode, a dielectric film and an upper electrode; a selection transistor formed at the substrate; an electrically conductive plug for providing electrical connection between the selection transistor and the capacitor; and a diffusion barrier film provided between the electrically conductive plug and the lower electrode of the capacitor. The diffusion barrier film is a Ta.sub.x Si.sub.1-x N.sub.y film or a Hf.sub.x Si.sub.1-x N.sub.y film (where 0.2<x<1 and 0<y<1). The lower electrode includes an Ir film and an IrO.sub.2 film which are sequentially formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.