Synchronizing circuit for generating internal signal synchronized to external signal
US6313674A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 16, 2000 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Aug 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable delay line outputs a clock signal advanced in phase by a time corresponding to a sum tH+tL of a time tH required to output high level data from an OCD circuit and a time tL required to output low level data from the OCD circuit. A replica circuit for outputting low level data has the same configuration as a circuit portion of the OCD circuit through which low level data passes. The replica circuit outputs a start signal SSH for outputting high level data from the OCD circuit. Another replica circuit for outputting high level data has the same configuration as a circuit portion of the OCD circuit through which high level data passes. The replica circuit outputs a start signal SSL for outputting low level data from the OCD circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.