Variable delay circuit
US6313681A · kind A · utility
76Cited by
3References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 27, 1999 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Oct 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00293
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable delay circuit has a positive logic variable delay circuit which delays an edge of a signal which is input through an input terminal and a negative logic variable delay circuit which delays an edge of the signal input through an input terminal. Only an edge delayed in accordance with the set time is extracted from all the edges of a signal supplied from the positive logic variable delay circuit and all the edges of a signal supplied from the negative logic variable delay circuit in an extracting circuit of the variable delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.