Offset cancelled integrator
US6313685A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2000 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Apr 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/1865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An offset integrator and method are provided to induce integrator leakage while simultaneously latching and canceling its own offset. The method includes combining a first and second input signals with a part of the output signal of a different polarity to produce a charge signal. An accumulation of the charge signal on a plurality of storage components is used to reduce the offset component of the output signal and simultaneously inducing an integrator leak. A positive and negative components of the input signals are combined with a negative and positive offset components of the part of the output signal, respectively. The method liner includes modifying a positive and negative components of an in-phase and a quadrature signal. A reset signal may be provided to erase a plurality of memory locations. A gating scheme may be used to provide a predetermined signal to produce a two-phase, non-overlapping signal. The two-phase non-overlapping signal also produces a predetermined delayed two-phase, non-overlapping signal. The gating scheme provides proper timing signals without the use of complementary clock phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.