Method and apparatus for accelerating software decode of variable length encoded information
US6313766A · kind A · utility
12Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1998 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Jul 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to accelerate variable length decode is disclosed. The system includes a logic device to receive a bit stream of variable length encoded information. The logic device outputs a fixed length value corresponding to a variable length code received as part of the bit stream of the variable length encoded information. The system also includes a processor to receive the fixed length value. The processor to performs a write of a coefficient to a system memory device, the coefficient corresponding to the fixed length value received from the logic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.