Analogue to digital converter
US6313780A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1999 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Sep 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1225
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (40) for receiving a sampled and held current which is connected via a switch (S41) to a first current memory (M42) and via a switch (S40) to a second current memory (M41). The output of the second current memory (M41) is fed via a switch (S44) to one input of a summing junction (46). The output of the first current memory (M42) is fed via a switch (S42) to the input of a comparator (L44) whose output is clocked into a latch (L44) whose Q output is connected to an output (45) as the digital result of the conversion. The Q output of the latch (L44) is also connected to a digital to analogue converter (46) whose analogue output is fed to a second input of the summing junction 46 via a switch (S43) to form the analogue residue signal for application via output (47) to the next conversion stage in the pipeline. The stage has the advantage that the analogue signal is fed from stage to stage using only one current memory (M41) thus reducing transmission loss and that corruption of the analogue signal by comparator "kick back" is avoided …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.