Semiconductor memory device
US6314017A · kind A · utility
137Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2000 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Jul 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprising a write transistor with a gate connected to a write word line and with a first impurity region forming a source or drain connected to a bit line, a read transistor with a gate connected to a second impurity region forming a source or drain of the write transistor, a first impurity region connected to a read word line, and a second impurity region connected to a bit line, and a capacitor connected between the gate and the second impurity region of the read transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.