Semiconductor memory device for reducing parasitic resistance of the I/O lines
US6314038A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2001 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Jan 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells outputs a first data signal through an I/O line; an I/O line driving circuit for generating a second data signal by amplifying the first data signal, wherein the I/O line driving circuit is connected to the I/O lines; a data bus driving circuit connected to the I/O line driving circuit to generate a third data signal by amplifying the second data signal; a data bus precharge circuit; and a data bus connecting the data bus driving circuit to the data bus precharge circuit, wherein the data bus precharge circuit precharges the data bus to a predetermined voltage level before the third data signal is generated and transfers a voltage of the data bus to high or low level in accordance with a logic value of the third data signal when the third data signal is generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.