Circuit and method for timing recovery in digital communication receiver
US6314129A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 18, 1998 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Nov 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/042
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Circuit and method for timing recovery in a digital communication receiver for improving a BER performance and having a faster data transmission rate, the timing recovery circuit for recovering a synchronous timing signal of a PN code from an output of a matched filter in the digital communication receiver, including a power calculation circuit for receiving an output of the matched filter and calculating a power of a PN code signal for each sample period in each symbol period, a maximal power position detection circuit for detecting a sample position at which a symbol period has a maximum power value, a symbol position tracking circuit for tracking and setting an optimal symbol position value, a modulo counter for rotating as many as a number of samples in one symbol period in counting the samples for providing a reference position of samples, and a comparator for comparing the present symbol position value from the symbol position tracking circuit and a count value from the modulo counter, and generating a symbol clock when the present symbol position value and the count value are the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.