Floating-point arithmetic unit which specifies a least significant bit to be incremented
US6314442A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An object is to obtain a floating-point arithmetic unit with improved throughput. The floating-point arithmetic unit comprises a mantissa adder-subtracter portion (MAP) for performing arithmetic operation of mantissa data (A, B) in floating-point data, an increment portion (INP) for performing increment to a bit in the arithmetic result (D) which corresponds to the LSB when it is assumed that the MSB in the arithmetic result (D) is not shifted, a round-off decision portion (RJP) for deciding whether to round up the bit one place lower than the LSB, and a selector (S1) for selectively outputting the arithmetic result from the increment portion (INP) or the arithmetic result (D) from the mantissa adder-subtracter portion (MAP).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.