Apparatus and method for maintaining cache coherency in a memory system
US6314497A · kind A · utility
1Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1998 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Dec 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a computer system is disclosed. The computer system includes a processor, a memory, an inverting device, a storage device coupled to the inverting device and a device coupled to the storage device. The device receives byte enable information and inverted information and provides inverted byte enable information to the memory upon a write back operation to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.