Method for improving the assignment of circuit locations during fabrication
US6314547A · kind A · utility
7Cited by
13References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1998 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Sep 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method for improving circuit location assignment is capable of operating in the boolean, electrical and spatial (location) domains. Optimization of location assignment parameters can be performed simultaneously by determining a subset of nets or paths and generating sets of motions to improve these nets or paths. Once sets of motions have been generated, they are tested to determine the most beneficial movement for improving the given circuit parameter (e.g., wireability, timing, etc.).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.