Semiconductor package lead plating method and apparatus
US6315189A · kind A · utility
14Cited by
37References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Oct 13, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53191
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for uniformly solder plating leads on semiconductor packages wherein the leads are rotated during the solder plating process and the solder on the leads in planarized and solder between and bridging the leads is removed by the application of a hot gas to the device having the leads. The hot gas is preferably N.sub.2 which is inert to the process flow at the point in the process when it is utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.