Trench transistor with a self-aligned source
US6316806A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Mar 31, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench field-effect transistor with a self-aligned source. At least a portion of the source implantation dose (604) is implanted underneath the gate (610) of a trench transistor by implanting an a non-orthogonal angle to the sidewall (608) of the trench. In one embodiment, a slow diffuser, such as arsenic, is implanted to minimize the post-implant diffusion. The resulting structure ensures gate-source overlap, and a consistent, small, gate-source capacitance with a lower thermal budget for the resultant device. The narrow depth of the source, in conjunction with its unique L-shape, improves device ruggedness because the source doping does not compensate the heavy body doping as much as with conventional devices. In one embodiment, the substrate is rotated 180 degrees within the implanter to implant both sidewalls of a trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.