High performance test interface
US6316954A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Jul 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/07378
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test interface is used to connect an electronic device under test ("DUT"), such as a computer chip, to a tester. The interface utilizes a combination of spring forces and air pressure forces to extend and retract pogo pins, respectively. The pogo pins when extended contact conductive pads which are electrically connected to the DUT, perhaps via a DUT board. Springs are biased to extend the pins to contact the pads, and air pressure is used to retract the pins. Thus no air pressure or vacuum is required to maintain the pins in contact with the pads. When retracted, the pogo pins are shielded from damage by a shield, such as a board with holes in it for the pogo pins to pass through.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.