Method and apparatus for vertically locking input and output signals
US6316974A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2000 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Aug 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectable. Two Phase Locked Loops are connected in series to achieve vertical lock between the input and output frames. Locking the vertical sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the user's display preferences but may not precisely represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved. A free running oscillator measures the frequency of the incoming video and sends its output to a micro-controller that computes the divider required in the first Phase Locked Loop based on user selected output resolution. …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.