Predistortion circuit
US6316983A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 2000 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Dec 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/3241
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input signal is phase-inverted to supply the inverted signal to a gate of an FET. When the gate-source voltage Vgs decreases, the differential resistance Rds of the FET increases. Moreover, the differential resistance Rds also increases when the drain-source voltage Vds increases. That is, if the magnitude of the input signal from the signal source (2) increases, the gate-source voltage Vgs decreases and the drain-source voltage Vds increases, so that the differential resistance Rds varies largely. This compensates the non-linearity of the following saturation amplifier. Phase compensation is also effected with a capacitor (stray capacitor) or an inductor connected in parallel to the FET in corporation of the phase inverter. The phase inverter may be structured using the stray capacitances of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.