Low-power low-jitter variable delay timing circuit
US6316987A · kind A · utility
144Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Dec 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The timing circuit includes at least one delay element and its supply voltage is obtained from an active current source. The current source is a current mirror which is driven by a differential amplifier. The differential amplifier compares a voltage on the delay clement supply line to a voltage on a current control node connected to a voltage controlled current source. An RC compensating circuit may be coupled to the current control node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.