DC offset calibration for a digital switching amplifier
US6316992A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2000 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Jul 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An offset voltage calibration circuit for use with a digital switching amplifier. The calibration circuit includes an analog-to-digital converter for converting at least one DC offset voltage associated with the digital switching amplifier to digital offset data. A memory stores the digital offset data. Control circuitry controls the analog-to-digital converter. A digital-to-analog converter coupled to the memory receives the digital offset data and generates an offset compensation voltage for applying to an input port of the digital switching amplifier which thereby cancels at least a portion of the at least one DC offset voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.