Analog circuitry for start-up glitch suppression
US6316993A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/348
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for reducing speaker "pops" and "clicks" during power on and power off transitions of an op amp driver. The circuit includes an op amp 14 having a first input terminal adapted to be coupled to an input signal and a second input terminal adapted to be coupled to a reference potential. A speaker 22 is capacitively coupled to the output terminal of the op amp 14. Also included are a first current source 26 for coupling a first bias current to the op amp, and a second current source 24 for coupling a second bias current to the op amp, the first bias current being much greater than said second bias current. A switch 28, coupled between the op amp 14 and the first current source 26, is responsive to a mode control signal PWDN(bar) for enabling and inhibiting flow of the first bias current to the op amp 14. In a preferred embodiment, the op amp is an integrated circuit device, and is a metal oxide semiconductor (MOS) circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.