Overload recovery circuit and method
US6317000A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2001 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Jan 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/3016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An operational amplifier includes an input stage (13) receiving an input signal (Vin) and having first (14) and second (16) output terminals, and also includes an output stage (10) having a pull-up transistor (M11) and a pull-down transistor (M2). The pull-up transistor has a source coupled to a first supply voltage (V.sub.DD), a gate coupled to the first output terminal (14), and a drain coupled to an output conductor (22) conducting an output signal (Vout). The pull-down transistor (M2) has a source coupled to a second supply voltage (V.sub.SS), a gate coupled to the second output terminal (16), and a drain coupled to the output conductor (22). An AB control circuit (20) is coupled between the gates of the pull-up transistor and a pull-down transistor. A first overload recovery circuit (X) is coupled between the output conductor (22) and the gate of the pull-up transistor for limiting the voltage on the gate of the pull-up transistor in response to the output voltage (Vout) when the output voltage is within a first predetermined range of the first supply voltage (V.sub.DD). A second overload recovery circuit (Y) is coupled between the output conductor (22) and the gate of the pul…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.