Process of clock recovery during the sampling of digital-type signals
US6317005A · kind A · utility
4Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Apr 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process of clock recovery during the sampling of computer-type signals, wherein the sampling clock is generated from a phase locked loop or PLL which multiplies a given frequency by an integer number, includes gauging the position of the edges of the computer-type signals with respect to the sampling clock with the aid of an analog ramp triggered by the rising edges of the said signals in such a way as to obtain a first position-dependent value, carrying out a sampling clock phase correction and then carrying out a sampling clock frequency correction by using a processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.