Method and arrangement for gyration filtering with low power consumption
US6317016A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | May 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An arrangement of differential amplifying-type gyrators is used to implement a signal-filtering circuit with significantly reduced power consumption. One specific example implementation is directed to a signal-filtering circuit arrangement that uses a gyrator-type signal-filtering circuit to simulate a multiple-section LC ladder implementation. A plurality of transconductance cells are arranged to simulate the first inductance ladder section and at least one subsequent inductance ladder section. The first inductance ladder section is adapted to provide a gain of two or three. By setting the gain of the first section in this manner, the noise contribution of the subsequent sections is significantly lessened relative to the conventional implementation in which the gain of the first section is unity. Further, each of the first and subsequent inductance ladder sections has at least one associated capacitance value scaled to accommodate a feed-forward and feedback path through transconductance cells and each has at least one associated transconductance value scaled to accommodate impedance level and signal amplitude of the circuit arrangement. The present invention is especially advanta…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.