Horizontal phase-locked loop for video decoder
US6317161A · kind A · utility
31Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N9/641
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop is provided which is operable to lock the sampling clock (pixel clock) to the incoming horizontal sync pulse contained within composite video information. Two modes of operation, coarse lock mode and fine lock mode, are used in controlling the phase-locked loop. In the coarse lock mode, coarse corrections are made to a horizontal discrete time oscillator so that a fast lock may be achieve using the fine lock mode. Coarse corrections are based on a normalized sum of weighted pixels collected within a narrow gate window. Lock is achieved when the falling edge is centered within the window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.