Hierarchical depth cascading of content addressable memory devices
US6317350A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2000 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Jun 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus hierarchically cascades a number of memory devices to achieve a balance between the number of match flag inputs and the time required to generate the system match flag. In some embodiments, the number of match inputs required for each cascaded device and the time required to generate a system match flag are each logarithmically related to the number of cascaded devices. In one embodiment, an m-level hierarchy of groups are defined for up to n memory devices, where m=log.sub.2 n and m is an integer greater than 2. The first hierarchy is defined as including n/2 groups of 2 memory devices, the second hierarchy is defined as including n/4 groups of 4 memory devices, and so on, until a final hierarchy of one group is defined. Each group in a given hierarchical level includes a pair of groups from the preceding hierarchical level. At each hierarchical level, the match flag generated by the first of the group's pair may be provided to each of the CAM devices in the second of the group's pair. In other embodiments, at each hierarchical level, the match flag(s) generated by devices in the first of the pair defined in the previous hierarchical are selectively provided…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.