Associative cache memory capable of reconfiguring a K-way and N-set cache memory into a M-unit, K-way and N/M-set cache memory
US6317351A · kind A · utility
12Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 7, 2001 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Mar 7, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A K way cache memory having improved operational speed and reduced power consumption is provided. The cache memory includes M cache memory units, but only activates one of the units at a given time. Moreover, only one match line is activated corresponding to a way having a tag address that matches an externally provided tag address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.