Semiconductor integrated circuit
US6317353A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2000 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Mar 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power supply line is formed over a memory cell array which has arranged a plurality of memory cells using a metal wiring layer M1 which is disposed on the side closest to the memory cell array, of all the metal wiring layers. The power supply lines are formed over the memory cell array using not only an upper metal wiring layer M2 but the metal wiring layer M1 so that the wiring resistance of the power supply lines may decrease and a sufficient amount of current can be supplied to the power supply lines. Consequently, the circuits supplied with an electric current through the power supply lines become capable of high-speed operation. This is particularly effective for the high-speed operation of the circuits arranged around the memory cell array. The power supply line formed using the lower metal wiring layer M1 is connected over the memory cell array to a power supply line which is formed using the metal wiring layer M2 on the upper layer than the metal wiring layer M1. Therefore, the netlike configuration of the power supply lines can be made with higher density compared to conventional ones.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.