Method and apparatus for adaptive port buffering
US6317427A · kind A · utility
71Cited by
5References
78Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1997 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Apr 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A data buffering storage circuit automatically allocates a portion of shared storage area to the direction in which data buffering is required. This scheme allows use of fewer parts on a piece of networking hardware, which in turn lowers the cost, simplifies the design, and uses existing on-board memory in a more efficient manner. In at least one embodiment, a first area is allocated to the buffering of a first port of a network switch, a second memory area is allocated to the buffering of a second port of the network switch, and a third area is shared among the buffering of the first port and the buffering of the second port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.