Viterbi decoder
US6317472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 1998 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Aug 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for providing and storing a state metric which is used for an add-compare-select (ACS) operation in a Viterbi decoder using a number of ACS units in order to enhance decoding speed. A state metric memory in Viterbi decoder uses a two-port memory, in which a memory bank for reading and writing a state metric of a first half among the N state metrics generated in a ACS unit and two memory banks for alternately reading and writing the state metric of the second half whenever a codeword is input, are incorporated into a single memory. As a result, the storage capacity for storing the state metrics can be greatly reduced as compared to a conventional apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.