Microprocessor comprising bit concatenation means
US6317825A · kind A · utility
3Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 3, 2000 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | May 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a microprocessor (MP) comprising means to decode (DEC1) a compact instruction (BMV) for the concatenation of at least one bit (b.sub.i) of a first binary word (W1) with at least one bit of a second binary word (W2), and means (REGBANK, MUX, BSHIFT) to process this instruction in one clock cycle. Advantages: fast processing of a concatenation operation. Application especially to chip cards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.