Method and apparatus for fault tolerant flash upgrading
US6317827A · kind A · utility
55Cited by
11References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1996 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Aug 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel method for upgrading a first program sequence in a computer system such that the computer system remains operable even if the upgrade process results in an incorrectly stored program sequence. The method uses the steps of storing the second program sequence in a second region of a memory, determining whether the second program sequence is stored correctly, and enabling the second program sequence if it is stored correctly. The first program sequence remains enabled if the second program sequence is not stored correctly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.