Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage

US6319780A · kind A · utility

Assignee

• STMicroelectronics SA

Inventors

• Barbara Crivelli · Milano, IT
• Daniela Peschiaroli · Milano, IT
• Elisabetta Palumbo · Bernareggio, IT
• Nicola Zatelli · Bergamo, IT

Key dates

• Filing date: Nov 29, 2000
• Grant date: Nov 20, 2001
• Expiry date: Nov 29, 2020

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/981

Abstract

Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.