Integrated circuit wiring and fabricating method thereof
US6319806A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 7, 2000 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Dec 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an integrated circuit wiring capable of reducing the contact resistance between lines and a fabricating method thereof. The wiring in accordance with the present invention includes a gate oxide film formed on the upper surface of a semiconductor device. A first line including a first silicon film pattern that is formed on an upper surface of the gate oxide film and has a certain width; and a silicide film pattern that is formed on the upper surface of the first silicon film and has a smaller width than that of the first silicon film pattern to thereby expose a certain region of the first silicon film pattern. A second line is formed to contact the silicide film pattern and the exposed certain region of the silicon film pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.