Sub-nanoscale electronic devices and processes
US6320200A · kind A · utility
53Cited by
39References
4Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Feb 1, 1996 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Feb 1, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure including a plurality of transistors; a plurality of thin-film conductor interconnects, interconnected to form electronic circuits in a predetermined electrical configuration; and a plurality of pairs of contact pads, connected to the thin-film conductor interconnects, each adjacent pair of contact pads including a first pad of a first conductive material and a second pad of a second conductive material, and being electrically connected only by a conductive oligomer of a precisely determined number of units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.