Semiconductor device having a ferroelectric TFT and a dummy element
US6320214A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1998 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Dec 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
Abstract
The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 .mu.m to 14 .mu.m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collision of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.