Architecture and interconnect for programmable logic circuits
US6320412A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved programmable logic device and interconnect architecture is provided. In one embodiment an interconnect network provides programmable routing between calls. In one embodiment the interconnect network includes first routing lines of a first level of routing lines, second routing lines of a second level of routing lines and third routing lines of a third level of routing lines. The first and second routing lines are programmably and bidirectionally coupled to the third routing lines such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from the third routing lines to the first routing lines and second routing lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.