Lock detector for phase-locked loop
US6320469A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2000 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Feb 15, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and lock detector for detecting lock between a reference signal and a feedback signal of a PLL circuit. A number of clock cycles of the feedback signal is counted during consecutive test intervals defined by the reference signal. A feedback comparator determines whether the number of clock cycles of the feedback signal during a given test interval is within an expected range. Before lock has been indicated, a qualification counter is either incremented or reset after each test interval in accordance with the expected range determination. A lock indication signal indicating that lock has been achieved is provided if said qualification counter exceeds a qualification threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.